17. CPU Exceptions

17.4 MIPSIV Instructions

The system must either be in Kernel or Supervisor mode, or have set the XX bit of the Status register to a 1 in order to use the MIPS IV instruction set. In User mode, if XX is a 0 and an attempt is made to execute MIPS IV instructions, an exception will be taken. The type of exception that will be taken depends upon the type of instruction whose execution was attempted; a list is given in Table 17-4. Note that operating with MIPS IV instructions does not require that MIPS III instruction set or 64-bit addressing is enabled.

MIPS IV instructions that use or modify the floating-point registers (CP1 state) are also affected by the CU1 bit of the CP0 Status register. If CU1 is not set, a Coprocessor Unusable exception may be signaled.

The Reserved Instruction (RI), Coprocessor Unusable (CU), and Unimplemented Operation (UO) exceptions for MIPS IV instructions are listed in the Table 17-4 below.

Table 17-4 MIPS IV Instruction Exceptions

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